TSV reveal etch for 3D integration

2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Volumn , Issue , 2011, Pages

  Olson, Stephen ^a,b   Hummler, Klaus ^a  

^a SEMATECH   (United States)

^b STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

3D Integration; Through Silicon Via (TSV); Wafer thinning

Indexed keywords

3-D INTEGRATION; BOND LAYER; CARRIER WAFERS; CMP PROCESS; ETCH PARAMETERS; THINNING PROCESS; THROUGH-SILICON-VIA; VIA-FIRST; WAFER THINNING; WET AND DRY;

INTEGRATION; SILICON WAFERS; THREE DIMENSIONAL COMPUTER GRAPHICS;

WAFER BONDING;

EID: 84866852066     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2012.6262987     Document Type: Conference Paper

References (4)

1. Halder, S., Jourdain, A., Claes, M., De Wolf, I., Travaly, Y., Beyne, E., et al, "Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's," Electronic Components and Technology Conference, 2011
2. Teh, W. H., Caramto, R., Qureshi, J., Arkalgud, S., O'Brien, M., Gilday, T., et al. "A route towards production-worthy 5 μm x 25 μm and 1 μm x 20 μm non-bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration," IEEE International Conference on 3D System Integration, 3DIC 2009
3. Lee, J., Lee, V., Seetoh, J., Thew, S. M. L., Yeo, Y. C., Li, H. Y., et al. (2011). "Advanced wafer thinning and handling for through silicon via technology," Electronic Components and Technology Conference, 2011
4. Kwon, W., Lee, J., Lee, V., Seetoh, J., Yeo, Y., Khoo, Y., et al, "Novel thinning/backside passivation for substrate coupling depression of 3D IC," Electronic Components and Technology Conference, 2011