Phase-locked loop based on selective harmonics elimination for utility applications

IEEE Transactions on Power Electronics

Volumn 28, Issue 1, 2013, Pages 144-153

  Ama, Naji Rajai Nasri ^a   Martinz, Fernando Ortiz ^a   Matakas, Lourenço ^a   Kassab, Fuad ^a  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

Author keywords

Field programmable gate arrays (FPGA); phase locked loops (PLL); power electronics

Indexed keywords

DISTORTED GRID VOLTAGE; PHASE ERROR; SELECTIVE HARMONICS ELIMINATIONS; SQUARE WAVEFORM; SQUARE WAVES; STEADY STATE; TRANSIENT TESTS;

DYNAMIC RESPONSE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); OSCILLISTORS; PHASE LOCKED LOOPS; POWER ELECTRONICS;

DELAY CIRCUITS;

EID: 84866518862     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2012.2195506     Document Type: Article

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