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Volumn , Issue , 2008, Pages 501-524

ATE interconnect performance to 43Gbps using advanced PCB materials

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS OF VARIOUS; AUTOMATED TEST EQUIPMENT; DATA RATES; INTERCONNECT PERFORMANCE; PATH LENGTH; SIGNAL INTEGRITY; SIGNAL PATHS; TEST FIXTURE;

EID: 84866405553     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (14)
  • 2
    • 0036443154 scopus 로고    scopus 로고
    • New paradigm for signal paths in ATE pin electronics are needed for serialcom device testing
    • Masashi Shimanouchi, "New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing, " Proceedings of the International Test Conference 2002.
    • (2002) Proceedings of the International Test Conference
    • Shimanouchi, M.1
  • 3
    • 84889950317 scopus 로고    scopus 로고
    • Proper PCB stackup and trace geometry design are key elements in the fight to lower losses
    • Jeff Loyer, "Proper PCB Stackup and Trace Geometry Design are Key Elements in the Fight to Lower Losses", Printed Circuit Design & Manufacture 2006.
    • (2006) Printed Circuit Design & Manufacture
    • Loyer, J.1
  • 9
    • 84889949229 scopus 로고    scopus 로고
    • Basics of measuring the dielectric properties of materials
    • PN 5989-2589EN
    • "Basics of Measuring the Dielectric Properties of Materials" Agilent Application Note, PN 5989-2589EN.
    • Agilent Application Note
  • 13
    • 84889913867 scopus 로고    scopus 로고
    • Passive equalization of test fixture for high-speed digital measurements with automated test equipment
    • Jose Moreira et al., "Passive Equalization of Test Fixture for High-Speed Digital Measurements with Automated Test Equipment, " Proceedings of the 2006 International Design and Test Workshop.
    • Proceedings of the 2006 International Design and Test Workshop
    • Moreira, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.