Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Microelectronic Engineering

Volumn 98, Issue , 2012, Pages 355-358

  Sacchetto, Davide ^a   Xie, Shenqi ^a   Savu, Veronica ^a   Zervas, Michael ^a   De Micheli, Giovanni ^a   Brugger, Jürgen ^a   Leblebici, Yusuf ^a  

^a EPFL   (Switzerland)

Author keywords

Ambipolarity; FET; Schottky barrier; Si nanowire; Silicide; Stencil lithography

Indexed keywords

AMBIPOLARITY; FET; SCHOTTKY BARRIERS; SI NANOWIRE; STENCIL LITHOGRAPHY;

ASPECT RATIO; FABRICATION; FIELD EFFECT TRANSISTORS; GALLIUM ALLOYS; INDUCTIVELY COUPLED PLASMA; NANOWIRES; SCHOTTKY BARRIER DIODES; SILICIDES; SURFACE TOPOGRAPHY;

POLYSILICON;

EID: 84865603597     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2012.07.048     Document Type: Conference Paper

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