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Volumn 83, Issue 3, 2012, Pages 338-343

An FPGA based hardware architecture for network flow analysis

Author keywords

Flow identifier; Flow monitor; FPGA; HNFA (Hardware network flow analyser)

Indexed keywords


EID: 84865450665     PISSN: 1450216X     EISSN: 1450202X     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (2)

References (8)
  • 4
    • 37249080197 scopus 로고    scopus 로고
    • Flow monitoring in high-speed networks with 2D hash tables
    • Field-Programmable Logic and Applications
    • D.Nguyen, J.Zambreno, and G.Memik, "Flow monitoring in high speed networks with 2D hash tables," Field Program. Logic application, vol.3203. pp.1093-1097, 2004. (Pubitemid 39210609)
    • (2004) Field Program. Logic Application , Issue.3203 , pp. 1093-1097
    • Nguyen, D.1    Zambreno, J.2    Memik, G.3
  • 5
    • 39749103465 scopus 로고    scopus 로고
    • Low power design of precomputation-Based content addressable memory
    • Mar
    • Shang-Jang Ruan, Chi-Yu wu and Jui-Yuan Hsieh, "Low power design of precomputation-based content addressable memory," in IEEE transactions on Vlsi .vol 16.,Mar 2008.
    • (2008) IEEE Transactions on Vlsi , vol.16
    • Ruan, S.-J.1    Wu, C.-Y.2    Hsieh, J.-Y.3
  • 8
    • 62949240224 scopus 로고    scopus 로고
    • Xilinx systems, version 5, Feb
    • Xilinx systems "Virtex V family overview," version 5, Feb 2009.,www.xilinx.com/support/documentation.
    • (2009) Virtex V Family Overview


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.