Germanium channel P-MOSFET with TiO 2/Al 2O 3 bilayer high-K gate stacks and solutions for metal/TiO 2 interface stability

2012 International Silicon-Germanium Technology and Device Meeting, ISTDM 2012 - Proceedings

Volumn , Issue , 2012, Pages 42-43

  Zhang, Liangliang ^a   Gungi, Marika ^a   McIntyre, Paul C ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BI-LAYER; CAPACITANCE-EQUIVALENT THICKNESS; CMOS DEVICES; DEVICE FABRICATIONS; GATE LEAKAGE CURRENT DENSITY; GATE STACKS; HIGH-K GATE STACKS; INTERFACE STABILITIES; INTERFACIAL LAYER; K-VALUES; METAL GATE; MOSFETS; PMOSFET; SI TECHNOLOGY; TIO;

ALUMINUM; CMOS INTEGRATED CIRCUITS; LOGIC GATES; MOSFET DEVICES; TITANIUM DIOXIDE;

GERMANIUM;

EID: 84864215666     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISTDM.2012.6222448     Document Type: Conference Paper

References (4)

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2. S. Gupta et al., "GeSn technology: Extending the Ge electronics roadmap," Tech. Dig. - Int. Elect. Dev. Meet., pp. 398, 2011.
3. G. Han et al., "High-mobility germanium-tin P-channel MOSFETs featuring metallic source/drain and sub-370 °C process modules," Tech. Dig. - Int. Elect. Dev. Meet., pp. 402, 2011.
4. x alloys on Ge-buffered Si (001) substrates," J. Crystal Growth, vol. 317, pp. 43, 2011.