Verification of floating-point adders

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1427 LNCS, Issue , 1998, Pages 488-499

  Chen, Yirng An ^a   Bryant, Randal E ^a  

^a Carnegie Mellon Univ ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; DIGITAL ARITHMETIC; SPECIFICATIONS;

CIRCUIT IMPLEMENTATION; DOUBLE PRECISION; FLOATING-POINT ADDER; REUSABLE SPECIFICATIONS; SHORT CIRCUITING; SYMBOLIC SIMULATION; UNIVERSITY OF MICHIGAN; VERIFICATION TASK;

ADDERS;

EID: 84863975140     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0028769     Document Type: Conference Paper

References (17)

1. BROCK, B., KAUFMANN, M., AND MOORE, J. S. ACL2 theorems about commerical microprocessors. In Proceedings of the Formal Methods on Computer-Aided Design (November 1996), pp. 275-293.
2. BRYANT, R. E. Graph-based algorithms for boolean function manipulation. In IEEE Transactions on Computers (August 1986), pp. 8:677-691.
3. BRYANT, R. E., AND CHEN, Y.-A. Verification of arithmetic circuits with binary moment diagrams. In Proceedings of the 32nd ACM/IEEE Design Automation Conference (June 1995), pp. 535-541.
4. CARREno, V. A., AND MINER, P. S. Specification of the IEEE-854 floating-point standard in HOL and PVS. In High Order Logic Theorem Proving and Its Applications (September 1995).
5. *PHDD: An efficient graph representation for floating point circuit verification. In Proceedings of the International Conference on Computer-Aided Design (November 1997), pp. 2-7.
6. CHEN, Y.-A., AND BRYANT, R. E. Verification of floating-point adders. Tech. Rep. CMU-CS-98-121, School of Computer Science, Carnegie Mellon University, 1998.
7. CHEN, Y.-A., CLARKE, E. M., HO, P.-H., HOSKOTE, Y, KAM, T., KHAIRA, M., O'LEARY, J., AND ZHAO, X. Verification of all circuits in a floating-point unit using word-level model checking. In Proceedings of the Formal Methods on Computer-Aided Design (November 1996), pp. 19-33. (Pubitemid 126149746)
8. CLARKE, E. M., FUJITA, M., AND ZHAO, X. Hybrid decision diagrams overcoming the limitations of MTBDDs and BMDs. In Proceedings of the International Conference on Computer-Aided Design (November 1995), pp. 159-163.
9. CLARKE, E. M., KHAIRA, M., AND ZHAO, X. Word level model checking - Avoiding the Pentium FDIV error. In Proceedings of the 33rd ACM/IEEE Design Automation Conference (June 1996), pp. 645-648.
10. COE, T. Inside the Pentium Fdiv bug. Dr. Dobbs Journal (April 1996), pp. 129-135.
11. COUDERT, O., AND MADRE, J. C. A unified framework for the formal verification of sequential circuits. In Proceedings of the International Conference on Computer-Aided Design (November 1990), pp. 126-129. (Pubitemid 21675482)
12. FISHER, L. M. Flaw reported in new intel chip. New York Times (May 6 1997), D, 4:3.
13. HAMAGUCHI, K., MORITA, A., AND YAJIMA, S. Efficient construction of binary moment diagrams for verifying arithmetic circuits. In Proceedings of the International Conference on Computer-Aided Design (November 1995), pp. 78-82.
14. HUFF, T. R. Architectural and circuit issues for a high clock rate floating-point processor. PhD Dissertation in Electrical Engineering Department, University of Michigan (1995).
15. JAIN, P., AND GOPALAKRISHNAN, G. Efficient symbolic simulation-based verification using the parametric form of boolean expressions. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (August 1994), pp. 1005-1015.
16. MCMILLAN, K. L. Symbolic Model Checking. Kluwer Academic Publishers, 1993.
17. QUACH, N., AND FLYNN, M. Design and implementation of the SNAP floating-point adder. Tech. Rep. CSL-TR-91-501, Stanford University, December 1991.