Identifying optimal multicore cache hierarchies for loop-based parallel programs via reuse distance analysis

Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, MSPC'12

Volumn , Issue , 2012, Pages 2-11

  Wu, Meng Ju ^a   Yeung, Donald ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Cache performance; Chip multiprocessors; Reuse distance

Indexed keywords

CACHE HIERARCHIES; CACHE PERFORMANCE; CHIP MULTIPROCESSOR; EXTENSIVE SIMULATIONS; MULTI CORE; PARALLEL PROGRAM; PROBLEM SIZE; REUSE DISTANCE; SHARED CACHE;

COMPUTER PROGRAMMING LANGUAGES; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS; SYSTEMS ANALYSIS;

OPTIMIZATION;

EID: 84863446439     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2247684.2247687     Document Type: Conference Paper

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