Low-temperature PEALD ZnO double-gate TFTs

2011 International Semiconductor Device Research Symposium, ISDRS 2011

Volumn , Issue , 2011, Pages

  Li, Yuanyuan V ^a   Ramirez, J Israel ^a   Li, Haoyu U ^a   Jackson, Thomas N ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOTTOM GATE; CIRCUIT APPLICATION; DEVICE PERFORMANCE; DOUBLE GATE; FLEXIBLE POLYMERIC SUBSTRATES; HIGH QUALITY; LINEAR REGION; LOW PROCESS TEMPERATURE; LOW TEMPERATURES; PLASMA-ENHANCED ATOMIC LAYER DEPOSITION; PLASTIC SUBSTRATES; PROCESS TEMPERATURE; SUBTHRESHOLD SLOPE; THRESHOLD VOLTAGE TUNING; TOP GATE; ZNO;

ATOMIC LAYER DEPOSITION; POLYIMIDES; THIN FILM TRANSISTORS; THRESHOLD VOLTAGE; ZINC OXIDE;

FABRICATION;

EID: 84863183167     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2011.6135191     Document Type: Conference Paper

References (4)

1. S. Kyoung-Seok, J. Ji-Sim, L. Kwang-Hee, K. Tae-Sang, P. Joon-Seok, C. Yun-Hyuk, P. KeeChan, K. Jang-Yeon, K. Bonwon, and L. Sang-Yoon, "Characteristics of Double-Gate Ga-In-Zn-O Thin-Film Transistor, " IEEE Electron Device Letters, 31, pp. 219-221 (2010).
2. H.-W. Zan, W.-T. Chen, C.-C. Yeh, H.-W. Hsueh, C.-C. Tsai, and H.-F. Meng, "Dual gate indium-galliumzinc-oxide thin film transistor with an unisolated floating metal gate for threshold voltage modulation and mobility enhancement, " Applied Physics Letters, 98, 153506 (2011).
3. D. A. Mourey, D. A. L. Zhao, J. Sun, and T. N. Jackson, "Fast PEALD ZnO Thin-Film Transistor Circuits, " IEEE Transactions on Electron Devices, 57, pp. 530-534 (2010).
4. D. L. Zhao, D. A. Mourey, and T. N. Jackson, "Fast Flexible Plastic Substrate ZnO Circuits, " IEEE Electron Device Letters, 31, pp. 323-325, (2010).