P-Type tunneling transistors with polycrystalline silicon by sequential lateral solidification growth technique

Japanese Journal of Applied Physics

Volumn 51, Issue 2 PART 2, 2012, Pages

  Lee, Min Hung ^a   Weng, Ssu Chieh ^a  

^a NATIONAL TAIWAN NORMAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE LAYER; AVALANCHE EFFECTS; BAND TO BAND TUNNELING; CONSTANT CURRENT STRESS; DISPLAY BACKPLANES; ELECTRICAL CHARACTERISTIC; GROWTH TECHNIQUES; LOW-LEAKAGE CURRENT; OFF-CURRENT; P-TYPE; POLYCRYSTALLINE SILICON (POLY-SI); SEQUENTIAL LATERAL SOLIDIFICATIONS; TEMPERATURE DEPENDENCE; THREE DIMENSIONAL INTEGRATED CIRCUITS; TUNNELING CURRENT;

ELECTRON TUNNELING; MICROWAVE CIRCUITS; MICROWAVE DEVICES; POLYSILICON; SOLIDIFICATION;

TRANSISTORS;

EID: 84863157694     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.51.02BJ13     Document Type: Article

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