MTJ based non-volatile flip-flop in deep submicron technology

2011 International SoC Design Conference, ISOCC 2011

Volumn , Issue , 2011, Pages 424-427

  Jung, Youngdon ^a   Kim, Jisu ^a   Ryu, Kyungho ^a   Jung, Scong Ook ^a   Kim, Jung Pill ^b   Kang, Seung H ^b  

^a Yonsei University   (South Korea)

^b QUALCOMM INC   (United States)

Author keywords

Leakage current; MTJ; Non volatile flip flop; Write current

Indexed keywords

FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; NAND CIRCUITS;

DEEP SUB-MICRON TECHNOLOGY; HSPICE SIMULATIONS; LOW-POWER SYSTEMS; MODEL PARAMETERS; NON-VOLATILE FLIP-FLOPS; RELIABILITY PROBLEMS; TECHNOLOGY SCALING; WRITE CURRENTS;

SPICE;

EID: 84863127302     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isocc.2011.6138622     Document Type: Conference Paper

References (6)

1. Anis, M. et al.,"Impact of technology scaling on CMOS logic styles", IEEE Trans. on Circuits and Systems II, Aug, 2002.
2. S. Shigematsu, S. Mutoh, Y. Matsuya and J. Yamada, "A 1-V high-speed MTCMOS circuit scheme for power-down applications," IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 861-869, Jun. 1997. (Pubitemid 127571557)
3. L.Wei, Z.Chen, K.Roy, M. C. Johnson, Y. Ye, and V. K. De, "Design and optimization of dual-threshold circuits for low-voltage low-power applications," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 7, no. 1, pp. 16-23, Feb. 1999.
4. Zhao, W. et al.,"New non-volatile logic based on spin-MTJ", physica status solidi (a), June, 2009.
5. Lakys, Y. et al.,"Low power, high reliability magnetic flip-flop", Electronics Letters, October, 2010.
6. Lin, C.J. et al.,"45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse connection 1T / 1MTJ cell", IEEE International Electron Devices Meeting(IEDM), Dec, 2009.