Realization of vertical resistive memory (VRRAM) using cost effective 3D process

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2011, Pages

  Baek, I G ^a   Park, C J ^a   Ju, H ^a   Seong, D J ^a   Ahn, H S ^a   Kim, J H ^a   Yang, M K ^a   Song, S H ^a   Kim, E M ^a   Park, S O ^a   Park, C H ^a   Song, C W ^a   Jeong, G T ^a   Choi, S ^a   Kang, H K ^a   Chung, C ^a  

^a New Memory Lab   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CELL LAYERS; CELL PROCESS; COST EFFECTIVE; MASS DATA; WET-ETCHING PROCESS;

CYTOLOGY; ELECTRON DEVICES; MEMORY ARCHITECTURE; TITANIUM NITRIDE; WET ETCHING;

COST EFFECTIVENESS;

EID: 84863017275     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2011.6131654     Document Type: Conference Paper

References (6)

1. ChiaHua Ho, Cho-Lun Hsu, Chun-Chi Chen, Jan-Tsai Liu, Cheng-San Wu, Chien-Chao Huang, Chenming Hu, and Fu-Liang Yang, "9nm Half-Pitch Functional Resistive Memory Cell with <1μA Programming Current Using Thermally Oxidized Sub-Stoichiometric WOx Film," IEDM Tech. Digest, p. 436, 2010.
2. M. J. Kim, I. G. Baek, Y. H. Ha, S. J. Baik, J. H. Kim, D. J. Seong, S. J. Kim, Y. H. Kwon, C. R. Lim, H. K. Park, D. Gilmer, P. Kirsch, R. Jammy, Y. G. Shin, S. Choi, and C. Chung, "Low Power Operating Bipolar TMO ReRAM for Sub 10 nm Era," IEDM Tech. Digest, p. 444, 2010.
3. I. G. Baek, D. C. Kim, M. J. Lee, H.-J. Kim, E. K. Yim, M. S. Lee, J. E. Lee, S. E. Ahn, S. Seo, J. H. Lee, J. C. Park, Y. K. Cha, S. O. Park, H. S. Kim, I. K. Yoo, U-In Chung, J. T. Moon and B. I. Ryu, "Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application," IEDM Tech. Digest, p. 750, 2005.
4. Christophe Chevallier, Chang Siau, Dennis Lim, Sri Namala, Misako Matsuoka, Bruce Bateman, Darrell Rinerson, "A 0.13μm 64Mb Multi- Layered Conductive Metal-Oxide Memory," ISSCC Tech. Digest, p. 260, 2010.
5. Hong Sik Yoon, In-Gyu Baek, Jinshi Zhao, Hyunjun Sim, Min Young Park, Hansin Lee, Gyu-Hwan Oh, Jong Chan Shin, In-Seok Yeo, and UIn Chung, "Vertical Cross-point Resistance Change Memory for Ultra- High Density Non-volatile Memory Applications," VLSI Tech. Digest, p. 26, 2009.
6. J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J.-H. Jeong, B.-K. Son, D. W. Kim, K. Kim, J.-J. Shim, J. S. Lim, K.-H. Kim, S. Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, S. Hwang, J.-W. Lee, Y.-H. Son, U-In Chung and W.-S. Lee, "Vertical Cell Array using TCAT(Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory," VLSI Tech. Digest, p. 192, 2009.