Analysis of 7T SRAM cell with SNM 0n 45nm technology for increasing cell stability

Proceedings of the International Conference on Nanoscience, Engineering and Technology, ICONSET 2011

Volumn , Issue , 2011, Pages 370-372

  Singh, Madhav ^a   Tomar, Shelendra Singh ^a  

^a ITM UNIVERSITY   (India)

Author keywords

CMOS; Data Stability; Read margin; Static Noise Margin; Write margin

Indexed keywords

45NM TECHNOLOGY; CELL OPERATION; CELL STABILITY; CMOS; PULL UP; READ MARGIN; SRAM CELL; SRAM CELL STABILITY; STATIC NOISE MARGIN; SUPPLY VOLTAGES; WRITE MARGIN; DATA STABILT;

NANOSCIENCE; CYTOLOGY; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

STATIC RANDOM ACCESS STORAGE; CELLS;

EID: 84862870386     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICONSET.2011.6167983     Document Type: Conference Paper

References (5)

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3. J Zory and A.welling , "Static noise margin analysis of sub threshold SRAM cells in deep submicron technology," Lecture Notes in Computer Science, vol. 3728, pp. 488-497 2005.
4. A. Pavlov & M.Sachdev, "CMOS SRAM CircuitDesign and Parametric Test in Nano-Scaled Technologies".Intel Corporation, University of Waterloo, 2008 SpringerScience and Business Media B.V., pp:1-202.
5. Aminulislam and Mohd Hassan "Variability analysis of 6T and 7T sram cellin sub-45nm technology"