Probabilistically programmed STT-MRAM

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volumn 2, Issue 1, 2012, Pages 42-51

  Wu, Wenqing ^a   Zhu, Xiaochun ^a   Kang, Seung ^a   Yuen, Kendrick ^a   Gilmore, Rob ^a  

^a QUALCOMM INC   (United States)

Author keywords

Arbitrarily small programming bit error rate (BER); high capacity spin transfer torque magnetoresistive random access memory (STT MRAM) chips; low power STT MRAM; multilevel cell (MLC) memory; probabilistic programming; stochastic switching

Indexed keywords

BIT ERROR RATES (BER); LOW POWER; MULTILEVEL CELL; PROBABILISTIC PROGRAMMING; SPIN TRANSFER TORQUE; STOCHASTIC SWITCHING;

BIT ERROR RATE; BODY SENSOR NETWORKS; FABRICATION; LOW POWER ELECTRONICS; MAGNETIC DEVICES; SWITCHING;

MRAM DEVICES;

EID: 84862809327     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2012.2187401     Document Type: Article

References (7)

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7. K. Ono et al., "A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM," in IEDM09-220, Baltimore, MD, 2009, pp. 219-222.