Design and performance of SMPs with asynchronous caches

HP Laboratories Technical Report

Volumn , Issue 149, 1999, Pages

  Pong, Fong ^a   Dubois, Michel ^a,b   Lee, Ken ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b University of Southern California ^*  (United States)

Author keywords

Asynchronous; Cache coherence; Shared memory multiprocessor; SMP

Indexed keywords

ASYNCHRONOUS DESIGNS; ILP PROCESSORS; INTERLOCKING PROTOCOL; SYMMETRIC MULTIPROCESSOR SYSTEMS (SMP);

BANDWIDTH; BUSES; CACHE MEMORY; COMPUTER HARDWARE; COMPUTER SIMULATION; NETWORK PROTOCOLS; PROGRAM PROCESSORS; SYSTEMS ANALYSIS; TELECOMMUNICATION LINKS;

MULTIPROCESSING SYSTEMS;

EID: 84862452056     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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