Hardware implementation techniques for recursive calls and loops

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1673, Issue , 1999, Pages 450-455

  Maruyama, Tsutomu ^a   Takagi, Masaaki ^a   Hoshino, Tsutomu ^a  

^a UNIVERSITY OF TSUKUBA   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

APPLICATION AREA; CIRCUIT SIZE; CLOCK CYCLES; COMBINATORIAL PROBLEM; GATE ARRAYS; HARDWARE IMPLEMENTATIONS; MULTI-THREAD; SPECULATIVE EXECUTION;

COMPUTER CIRCUITS;

EID: 84862137248     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-48302-1_52     Document Type: Conference Paper

References (4)

1. Timothy J. Callahan and John Wawrzynek, “Instruction-Level Parallelism for Reconfigurable Computing”, Field-Programmable Logic and Applications, 1998, pp.248-257.
2. John R. Hauser and John Wawrzynek, “Garp: A MIPS Processor with a Reconfigurable Coprocessor”, FPGAs for Custom Computing Machines, 1997 pp.12-21.
3. Ralph D. Witting and Paul Chow, “OneChip: An FPGA processor with reconfigurable logic”, FPGAs for Custom Computing Machines, 1996 pp.126-135.
4. Niklaus Wirth, “Algorithms and data structures”, Prentice-Hall, 1986