A hybrid magnetic/complementary metal oxide semiconductor process design kit for the design of low-power non-volatile logic circuits

Journal of Applied Physics

Volumn 111, Issue 7, 2012, Pages

  Di Pendina, G ^a,b   Prenat, G ^b   Dieny, B ^b   Torki, K ^a  

^a CMP Service   (France)

^b CEA GRENOBLE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPACT MODEL; CUTTING-OFF; ELECTRICAL SIMULATION; HYBRID CMOS; LOW POWER; MAGNETIC TUNNEL JUNCTION; METAL OXIDE SEMICONDUCTOR; MICROELECTRONIC CIRCUITS; MOORE'S LAW; NON-VOLATILE; OPERATION FREQUENCY; POWER GATINGS; POWER SUPPLY; PROCESS DESIGN KIT; STANDARD CELL; STANDARD CMOS; STANDARD DESIGN;

CMOS INTEGRATED CIRCUITS; ELECTRIC BATTERIES; ELECTRIC POWER SYSTEMS; LOGIC CIRCUITS; MAGNETIC DEVICES; MICROELECTRONICS; MOS DEVICES; PROCESS DESIGN;

LOGIC DESIGN;

EID: 84861748586     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3680013     Document Type: Conference Paper

References (7)

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