Area scaling analysis of CMOS ADCs

Electronics Letters

Volumn 48, Issue 6, 2012, Pages 314-315

  Verhelst, M ^a   Murmann, B ^b  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA SCALING; HISTORICAL DATA;

ELECTRONICS ENGINEERING; TECHNOLOGY;

ANALOG TO DIGITAL CONVERSION;

EID: 84861586257     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el.2012.0253     Document Type: Article

References (5)

1. Dautriche, P.: ' Analog design trends and challenges in 28 and 20nm CMOS technology ', Proc. ESSCIRC, Helsinki, Finland, 2011, p. 1-4
2. Chiu, Y., Nikolic, B., and Gray, P.R.: ' Scaling of analog-to-digital converters into ultra-deep-submicron CMOS ', Proc. of the IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, 2005, p. 375-382
3. Jonsson, B.E.: ' Area efficiency of ADC architectures ', European Conf. on Circuit Theory and Design, Linkoping, Sweden, 2011, p. 560-563
4. Murmann, B.: ' ADC Performance Survey 1997-2012 ', [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
5. Ginsburg, B.P., and Chandrakasan, A.P.: ' The mixed signal optimum energy point: voltage and parallelism ', Design Automation Conf., Anaheim, CA, USA, 2008, p. 244-249