A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 434-435

  Oh, Tae Young ^a   Sohn, Young Soo ^a   Bae, Seung Jun ^a   Park, Min Sang ^a   Lim, Ji Hoon ^a   Cho, Yong Ki ^a   Kim, Dae Hyun ^a   Kim, Dong Min ^a   Kim, Hye Ran ^a   Kim, Hyun Joong ^a   Kim, Jin Hyun ^a   Kim, Jin Kook ^a   Kim, Young Sik ^a   Kim, Byeong Cheol ^a   Kwak, Sang Hyup ^a   Lee, Jae Hyung ^a   Lee, Jae Young ^a   Shin, Chang Ho ^a   Yang, Yun Seok ^a   Cho, Beom Sig ^a   Bang, Sam Young ^a   Yang, Hyang Ja ^a   Choi, Young Ryeol ^a   Moon, Gil Shin ^a   Park, Cheol Goo ^a   Hwang, Seok Won ^a   Lim, Jeong Don ^a   Park, Kwang Il ^a   Choi, Joo Sun ^a   Jun, Young Hyun ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

3D GRAPHICS; CHANNEL CROSSTALK; CROSS-TALK CANCELLER; HIGH BANDWIDTH; HIGHER RESOLUTION; MEMORY INTERFACE; PACKAGE ROUTING; PHYSICAL LIMITS; REALISTIC MODELING; REFERENCE VOLTAGES; SINGLE-ENDED; SPEED IMPROVEMENT; TRACE LENGTH;

CROSSTALK; POLYCHLORINATED BIPHENYLS; THREE DIMENSIONAL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 77952117178     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433889     Document Type: Conference Paper

References (4)

1. R. Kho, D. Boursin, M. Brox, et al, "75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques," Solid-State Circuits Conference - Digest of Technical Papers, 2009.8-12 Feb. 2009
2. Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park,Young-Hyun Jun, Joo Sun Choi, Kinam Kim, "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme," Solid-State Circuits Conference - Digest of Technical Papers, 2009. 8-12 Feb. 2009
3. E. Seevinck, van P. J. Beers, H. Ontrop, "Current-mode techniques for highspeed VLSI circuits with application to current sense amplifier for CMOS SRAM's," Solid-State Circuits, IEEE Journal of, Volume 26, Issue 4, April 1991
4. T. Tanzawa, S. Atsumi, "Optimization of word-line booster circuits for low-voltage flash memories," Solid-State Circuits, IEEE Journal of, Volume 34, Issue 8, Aug. 1999.