Robust decoder architecture for multi-level flash memory storage channels

2012 International Conference on Computing, Networking and Communications, ICNC'12

Volumn , Issue , 2012, Pages 492-496

  Motwani, Ravi ^a   Ong, Chong ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BEGINNING OF LIVES; CHANNEL DEGRADATIONS; CHANNEL DISTORTIONS; CHANNEL IMPAIRMENT; CHARGE LOSS; DECODER ARCHITECTURE; DECODING ALGORITHM; END OF LIVES; ERROR CONTROL CODING; FLOATING-GATES; GAUSSIAN PROBABILITY DENSITY FUNCTIONS; GAUSSIANS; HARDWARE COST; INDIVIDUAL CELLS; LDPC CODES; LDPC DECODER; LEVEL DISTRIBUTION; MEMORY CHANNELS; MEMORY STORAGE; MEMORY SYSTEMS; MULTI-LEVEL; MULTIPLE LEVELS; REALISTIC MODEL; SINGLE-BIT;

BIT ERROR RATE; CELLS; CYTOLOGY; ERROR CORRECTION; GAUSSIAN DISTRIBUTION; HARDWARE;

FLASH MEMORY;

EID: 84859887124     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCNC.2012.6167471     Document Type: Conference Paper

References (9)

1. J.D. Lee et-al., "Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation", IEDL, Vol. 23, No. 5, pp. 264- 266, 2002
2. J. Brewer et-al., "Nonvolatile Memory Technologies with Emphasis on Flash", IEEE Press Series on Microelectronic Systems, Chapter 6, 2008.
3. Jim Cooke, "The Inconvenient Truths of NAND Flash Memory," Flash Memory Summit 2007.
4. Juntan Zhang, Fossorier, M., Daqing Gu, Jinyun Zhang, "Improved min-sum decoding of LDPC codes using 2-dimensional normalization," Global Telecommunications Conference, 2005, GLOBECOM '05, IEEE, vol.3, no., pp. 6 pp., 28 Nov.-2 Dec. 2005.
5. A. Berman, Y. Birk, "Mitigating Inter-Cell Coupling Effects inMLCNAND Flash via Constrained Coding", Flash Memory Summit 2010.
6. R. Motwani, "Error Resilient constrained coding to overcome program disturb and SBCL impact," Intel IDF no. 83321 (patent application pending).
7. R. Motwani, "Misplacement mitigation using LDPC decoder modification," Intel IDF no. 85023, 82642 (patent application pending).
8. R. Motwani, "Mitigating the impact of Program Disturb and SBCL impairments using odd and even page level information,"Intel IDF no. 82732 (patent application pending).
9. R. Motwani, "Hierarchical Constrained Coding for Floating Gate Coupling Mitigation in Flash Memory," Proc. Global Telecommunications Conference, 2011, GLOBECOM '2011, IEEE.