Hierarchical constrained coding for floating-gate to floating-gate coupling mitigation in flash memory

GLOBECOM - IEEE Global Telecommunications Conference

Volumn , Issue , 2011, Pages

  Motwani, Ravi ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE COUPLINGS; CHANNEL NOISE; CONSTRAINED CODES; CONSTRAINED CODING; CONSTRAINED DECODING; DECODING ALGORITHM; DEGRADING FACTORS; ERROR PROPAGATION; FLOATING GATES; GRID OF CELLS; POSSIBLE SOLUTIONS; PROGRAMMING TIME; PROGRAMMING VOLTAGE; RECTANGULAR LATTICES; VOLTAGE LEVELS;

BANDPASS FILTERS; COMMUNICATION; CYTOLOGY; DECODING; FLASH MEMORY;

CELLS;

EID: 84857206093     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/GLOCOM.2011.6134528     Document Type: Conference Paper

References (4)

1. "Mitigating Inter-Cell Coupling Effects in MLC NAND Flash via Constrained Coding", Amit Berman and Yitzhak Birk, Flash Memory Summit 2010.
2. "Constrained Systems and Coding for Recording Channels," B. Marcus, R. Roth, and P. Siegel, Handbook of Coding Theory, Elsevier Scientific Publishers, 1998.
3. "A maximum-likelihood decoder for synchronization," Ravi Motwani, Intel IDF no. 83450 (patent application pending).
4. "Error Resilient constrained coding to overcome program disturb and SBCL impact," Ravi Motwani, Intel IDF no. 85023, 83321 (patent application pending).