IBM zEnterprise 196 microprocessor and cache subsystem

IBM Journal of Research and Development

Volumn 56, Issue 1-2, 2012, Pages

  Busaba, F ^a   Blake, M A ^a   Curran, B ^a   Fee, M ^a   Jacobi, C ^b   Mak, P K ^a   Prasky, B R ^a   Walters, C R ^a  

^a IBM   (United States)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BRANCH PREDICTION; CACHE HIERARCHIES; COMPUTING PROCESSORS; EMBEDDED DRAM; MEMORY SUBSYSTEMS; ONLINE TRANSACTION PROCESSING; OUT OF ORDER; PERFORMANCE GAIN; QUEUE MANAGEMENT; SILICON TECHNOLOGIES; SINGLE CYCLE; SYSTEM Z;

CACHE MEMORY; DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING;

INFORMATION TECHNOLOGY;

EID: 84859804834     PISSN: 00188646     EISSN: 21518556     Source Type: Journal    
DOI: 10.1147/JRD.2011.2173962     Document Type: Article

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