Server-class DDR3 SDRAM memory buffer chip

IBM Journal of Research and Development

Volumn 56, Issue 1-2, 2012, Pages

  Van Huben, G A ^a   Lamb, K D ^a   Tremaine, R B ^a   Aleman, B E ^a   Rubow, S M ^a   Rider, S H ^a   Maule, W E ^a   Wazlowski, M E ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP ARCHITECTURE; CYCLIC REDUNDANCY; DOUBLE DATA RATE; DYNAMIC CALIBRATION; ENGINEERING ASPECTS; ENVIRONMENTAL CONDITIONS; HIGH-CAPACITY; IN-LINE; LOW-LATENCY; MEMORY BUFFERS; MEMORY MODULES; MEMORY SUBSYSTEMS; MEMORY SYSTEMS; MULTI-CHANNEL; OPTIMAL SIGNALS; SDRAM MEMORY; SERVER PLATFORM; SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORIES; SYSTEM Z;

OPTIMAL SYSTEMS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84859799190     PISSN: 00188646     EISSN: 21518556     Source Type: Journal    
DOI: 10.1147/JRD.2011.2177897     Document Type: Article

References (10)

1. Cisco Inc., Cisco Unified Computing System Extended Memory Technology Overview, 2009. [Online]. Available: http://www. cisco.com/en/US/prod/ collateral/ps10265/ps10280/ps10300/white-paper-c11-525300.pdf
2. P. J. Meaney, L. Lastras-Montaño, V. K. Papazova, E. Stephens, J. S. Johnson, L. C. Alves, J. A. O'Connor, and W. J. Clarke, BIBM zEnterprise redundant array of independent memory subsystem,[ IBM J. Res. & Dev., vol. 56, no. 1/2, Paper 4, pp. 4:1-4:11, Jan./Mar. 2012.
3. JEDEC DDR3 Specification, JESD79-3E, Jul. 2010. [Online]. Available: http://www.jedec.org/sites/default/files/docs/JESD79-3E.pdf.
4. R. Reutemann, M. Ruegg, F. Keyser, J. Bergkvist, D. Dreps, T. Toifl, and M. Schmatz, BA 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS,[ IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2850-2860, Dec. 2010.
5. B. Schroeder, E. Pinheiro, and W. Weber, BDRAM errors in the wild: A large-scale field study,[ in Proc. 11th Int. Joint Conf. Meas. Model. Comput. Syst., SIGMETRICS, 2009, pp. 193-204. [Online]. Available: http://www.cs. toronto.edu/~bianca/papers/sigmetrics09.pdf.
6. J. Haas and P. Vogt. (2005, Mar.). Fully-buffered DIMM technology moves enterprise platforms to the next level. Technology@Intel Mag. [Online]. 3, pp. 1-7. Available: http://www.signallake.com/innovation/Fully-Buffered-DIMM-0305. pdf
7. Intel Inc., Intel 6400/6402 Advanced Memory Buffer Data Sheet, Oct. 2006. [Online]. Available: http://www.intel.com/assets/pdf/datasheet/313072.pdf
8. Increasing Computing Platform Efficiency Through Innovative Memory Architecture, Inphi Corporation iMB Technology white paper, Inphi, Nov. 2, 2009. [Online]. Available: http://www. gsaglobal.org/documents/2009/Inphi-111209.pdf
9. R. M. Nasr, BFBSIM and the fully buffered DIMM memory system architecture,[ M.S. thesis, Dept. Elect. Comput. Eng., Univ. Maryland, College Park, MD, 2005.
10. B. Ganesh, A. Jaleel, D. Wang, and B. Jacob, BFully-buffered DIMM memory architectures: Understanding mechanisms, overheads and scaling,[ in Proc. High Perform. Comput. Archit. Conf., Scottsdale, AZ, 2007, pp. 109-120. (Pubitemid 47208157)