Design and analysis of a hardware-efficient compressed sensing architecture for data compression in wireless sensors

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 3, 2012, Pages 744-756

  Chen, Fred ^a   Chandrakasan, Anantha P ^a   Stojanoviæ, Vladimir M ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Biomedical electronics; Circuit analysis; Compressed sensing; Electroencephalography; Encoding; Low power electronics; Sensors; Wireless sensor networks

Indexed keywords

BIOMEDICAL ELECTRONICS; COMPRESSED SENSING; ELECTROENCEPHALOGRAPHIES (EEG); LOW POWER; WIRELESS SENSOR NETWORK (WSN);

CMOS INTEGRATED CIRCUITS; DATA PROCESSING; DESIGN; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTROENCEPHALOGRAPHY; ELECTROPHYSIOLOGY; ENCODING (SYMBOLS); ENERGY EFFICIENCY; SENSORS; SIGNAL RECONSTRUCTION; SIGNAL SAMPLING;

DATA COMPRESSION;

EID: 84857804076     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2179451     Document Type: Article

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