A 130-μW, 64-channel spike-sorting DSP chip

Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Volumn , Issue , 2009, Pages 289-292

  Karkare, Vaibhav ^a   Gibson, Sarah ^a   Marković, Dejan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE DESIGNS; CLINICAL STUDY; CMOS PROCESSS; DATA-RATE; DSP CHIP; MATLAB /SIMULINK; MODULAR ARCHITECTURES; MULTI-CHANNEL; ON CHIPS; PERFORMANCE ANALYSIS; POWER CONSUMPTION; POWER DENSITIES; POWER DISSIPATION; PROCESSING STEPS; SINGLE CHANNELS; SPIKE DETECTION; SPIKE-SORTING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSORS; NEUROPHYSIOLOGY; SORTING; WATER WELL PUMPS;

FEATURE EXTRACTION;

EID: 76249106422     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2009.5357255     Document Type: Conference Paper

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