A scalable strategy for runtime resource management on NoC based manycore systems

2011 International Symposium on Integrated Circuits, ISIC 2011

Volumn , Issue , 2011, Pages 297-300

  Liao, Xiongfei ^a   Srikanthan, Thambipillai ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CENTRALIZED RESOURCES; COMMUNICATION CONTENTION; MANY-CORE; RESOURCE MANAGEMENT; RUNTIMES;

INTEGRATED CIRCUITS; NATURAL RESOURCES MANAGEMENT;

RESOURCE ALLOCATION;

EID: 84856741409     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISICir.2011.6131955     Document Type: Conference Paper

References (18)

1. K. Asanovic et al., The Landscape of Parallel Computing Research: A View from Berkeley. TR UCB/EECS-2006-183, U. C. Berkeley, 2006.
2. S. Borkar. Thousand Core Chips: A Technology Perspective. In DAC '07: Proc. of the 44th Design Automation Conference, 2007.
3. L. Benini et al., Networks on Chips: A New Paradigm for Component-Based MPSoC Design. In IEEE Computer, pp. 70-78., Jan. 2002. (Pubitemid 34069383)
4. C. Chou et al., Energy-and Performance-aware Incremental Mapping for Networks on Chip with Multiple Voltage Levels. CAD of Integr. Circuits and Syst., IEEE Trans. on, 27(10):1866-1879, Oct. 2008.
5. S. V. Tota et al., A Case Study for NoC-based Homogeneous MPSoC Architectures. IEEE Trans. VLSI Syst., 17(3):384-388, 2009.
6. C. Chou et al., Run-time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip. IEEE Trans. on CAD of Integr. Circuits and Syst., 29, 2010.
7. Tilera. TILE Processors, http://www.tilera.com, 2009.
8. X. Liao et al., A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM. Transactions on High-Performance Embedded Architectures and Compilers, Vol.4 (4), 2009.
9. X. Liao et al., A UNISIM Based Simulator Framework for NoC Based Manycore Systems. http://sourceforge.net/projects/nocsim-unisim.
10. M. Pastrnak et al., Parallel Implementation of Arbitrary-Shaped MPEG-4 Decoder for Multiprocessor Systems. Proc. Visual Comm. and Image Processing, 2006.
11. M. Azimi et al., Integration Challenges and Tradeoffs for Tera-Scale Architectures. Intel Technology Journal, Volume 11, Issue 3, 2007.
12. I. Ababneh. An Efficient Free-List Submesh Allocation Scheme for Two-Dimensional Mesh-Connected Multicomputers. Journal of Systems and Software, 79(8):1168-1179, 2006. (Pubitemid 44056081)
13. S. Bani-Mohammad et al., An Efficient Non-Contiguous Processor Allocation Strategy for 2D Mesh Connected Multicomputers. Information Sciences, 177(14), pages 2867-2883, 2007. (Pubitemid 46660014)
14. R. Dick, Embedded System Synthesis Benchmarks Suites (E3S)[online], available http://ziyang.eecs.umich.edu/~dickrp/e3s, 2010.
15. T. Ye et al., Analysis of Power Consumption on Switch Fabrics in Network Routers. In Proc. of DAC'02, 2002.
16. M. Bender et al., Communication-Aware Processor Allocation for Supercomputers: Finding Point Sets of Small Average Distance. Algorithmica, 50(2):279-298, 2008.
17. Vincent Nollet et al., Operating-System Controlled Network on Chip. In DAC '04: Proc. of the 41st Design Automation Conference, 2004.
18. G. Venkatesh et al., Conservation Cores: Reducing The Energy of Mature Computations. In Proc. of ASPLOS'10, 2010.