MCFQ: Leveraging memory-level parallelism and application's cache friendliness for efficient management of quasi-partitioned last-level caches

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2011, Pages 205-206

  Kaseridis, Dimitris ^a   Iqbal, Muhammad Faisal ^a   Stuecheli, Jeffrey ^a   J̃ohn, Lizy Kurian ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSOLUTE NUMBER; CACHE CAPACITY; CACHE MANAGEMENT SCHEMES; CACHE MISS; CHIP MULTIPROCESSOR; DESTRUCTIVE INTERFERENCE; FULL-SYSTEM SIMULATION; MEMORY-SHARING; SHARED CACHE; SYSTEM THROUGHPUT;

MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; PARALLEL ARCHITECTURES;

CACHE MEMORY;

EID: 84856535055     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2011.74     Document Type: Conference Paper

References (7)

1. A. Jaleel et al., "Adaptive insertion policies for managing shared caches". In Parallel Architectures and Compilation Techniques (PACT), pages 208-219, 2008.
2. Milo M. K. Martin et al. "Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset", Computer Architecture News (CAN), September 2005
3. M. K. Qureshi and Yale N. Patt, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches", In Symp. on Microarchitecture (MICRO), pages 423-432, 2006. (Pubitemid 351337015)
4. M. K. Qureshi, et al. "Adaptive Insertion Policies for High-Performance Caching", In Symposium on Computer Architecture (ISCA),pages 381-391, 2007. (Pubitemid 47582119)
5. Simics Microarchitect's Toolset, http://www.virtutech.com/
6. SPEC cpu2006 Benchmark Suit, http://www.spec.org
7. Yuejian Xie and Gabriel H. Loh, "PIPP: Promotion/Insertion Pseudo-partitioning of Multicore Shared Caches," In symposium on Computer architecture (ISCA), pages 174-183, 2009.