Elimination of drift-like errors in intelligent cyclic A/D converters

Measurement: Journal of the International Measurement Confederation

Volumn 45, Issue 2, 2012, Pages 170-174

  Jȩdrzejewski, Konrad ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Cyclic A D converters; Drift cancellation; Estimation algorithms

Indexed keywords

A/D CONVERTER; CMOS TECHNOLOGY; DIGITAL PARTS; DRIFT CANCELLATION; DRIFT RATES; ESTIMATION ALGORITHMS; INPUT SAMPLE; PRACTICAL REALIZATIONS; PRODUCTION COST; SAMPLE-AND-HOLD; SAMPLE-AND-HOLD CIRCUITS; SIMULATION EXPERIMENTS;

ALGORITHMS; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; ERRORS; EXPERIMENTS;

ANALOG TO DIGITAL CONVERSION;

EID: 84655167970     PISSN: 02632241     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.measurement.2011.03.021     Document Type: Article

References (15)

1. W. Kester Analog-Digital Conversion 2004 Analog Devices Inc.
2. M.E. Waltari, and K.A.I. Halonen Circuit Techniques for Low-voltage and High-speed A/D Converters 2002 Kluwer Academic Publishers
3. Specifications and Architectures of Sample-and-Hold Architectures, National Semiconductor Application Note 775, July 1992.
4. C. Fiocchi, U. Gatti, and F. Maloberti Design issues on high-speed high-resolution track-and-holds in BiCMOS technology IEE Proceedings Circuits Devices & Systems 147 2 2000 100 106
5. L.S.Y. Wong, S. Hossain, A. Walker, Leakage current cancellation technique for low power switched-capacitator circuits, in: Proceedings of International Symposium on Low Power Electronics and Design, Huntington Beach, California, USA, 2001, pp. 310-315. (Pubitemid 32806581)
6. A. Harb, A. Assi, A 10-MHz low-power always valid sample-and-hold circuit with low droop rate, in: Proceedings of 50th Midwest Symposium on Circuits and Systems, Montreal, Canada, 2007, pp. 156-158.
7. A.A. Platonov, K. Jȩdrzejewski, and J. Jasnos Design and analysis of algorithmic multi-pass A/D converters with theoretically highest resolution and rate of conversion Measurement 35 3 2004 277 287
8. A.A. Platonov, K. Jȩdrzejewski, LM. Małkiewicz, and J. Jasnos Principles of optimisation, modelling and testing of intelligent cyclic A/D converters Measurement 39 3 2006 213 231 (Pubitemid 43292340)
9. A.A. Platonov, J. Jasnos, K. Jȩdrzejewski, L. Małkiewicz, Z. Jaworski, E. Piwowarska, P. Studziński, Particularities of cyclic intelligent ADC design, implementation and adjusting, in: Proceedings of International Conference on Signals and Electronic Systems ICSES 2008, Cracow, Poland, 2008, pp. 43-46.
10. A.A. Platonov Optimal identification of regression-type processes under adaptively controlled observations IEEE Transactions on Signal Processing 42 9 1994 2280 2291
11. A.A. Platonov, J. Szabatin, and K. Jȩdrzejewski Optimal synthesis of smart measurement systems with adaptive correction of drifts and setting errors of the sensor's working point IEEE Transactions on Instrumentation and Measurement 47 3 1998 659 665 (Pubitemid 128738587)
12. J. Jasnos, Analysis and application of modified sub-optimal algorithms to ICADC design, in: 14th IMEKO Proceedings of International Symposium on New Technologies in Measurement and Instrumentation and 10th Workshop on ADC Modeling and Testing, Gdynia-Jurata, Poland, 2005, pp. 564-567.
13. L.M. Małkiewicz, A.A. Platonov, Methods of additional improvement of intelligent CADC performance, in: Proceedings of IEEE Instrumentation and Measurement Technology Conference, IMTC'2007, Warsaw, Poland, 2007, CD-ROM.
14. IEEE Std 1241-2000, IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Inc., 2001.
15. K. Jȩdrzejewski, A.A. Platonov, A new approach to cancellation of harmonic interferences in intelligent cyclic A/D converters, in: Proceedings of International Conference on Signals and Electronic Systems ICSES'10, Gliwice, Poland, 2010, pp. 41-45.