A 10-MHz low-power always valid sample-and-hold circuit with low-droop rate

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 156-158

  Harb, Adnan ^a   Assi, Ali ^a  

^a UNITED ARAB EMIRATES UNIVERSITY   (United Arab Emirates)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; COMPUTER NETWORKS;

HIGH DC GAIN; LOW POWERS; SAMPLE-AND-HOLD; SAMPLING FREQUENCIES;

NETWORKS (CIRCUITS);

EID: 51449115690     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2007.4488560     Document Type: Conference Paper

References (5)

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2. A. Harb, Y. Hu, and M. Sawan, "Low-power CMOS interface for recording and processing very low amplitude signals", Analog Integrated Circuits and Signal Processing, Vol. 39, pp. 39-54, April 2004.
3. R. Jacob Baker, CMOS circuit design, layout, and simulation, 2nd Ed., Wiley- IEEE, 2005.
4. K. Bult, and G. J. G. M. Geelen, "A fast settling CMOS op amp for SC circuits with 90-dB DC gain", IEEE JSSC, Vol. 25, No. 6, December 1990, pp. 1379- 1384.
5. U. Gatti, F. Maloberti, and G. Palmisano, "An accurate CMOS sample-and-hold circuit", IEEE JSSC, Vol. 27, No. 1, January 1992, pp. 120- 122.