-
1
-
-
83455197974
-
Making multi-cores mainstream - From security to scalability
-
IOS Press
-
C. Jesshope, M. Hicks, M. Lankamp, R. Poss, and L. Zhang, "Making multi-cores mainstream - from security to scalability," in Advances in Parallel Computing, vol. 18, IOS Press, 2010.
-
(2010)
Advances in Parallel Computing
, vol.18
-
-
Jesshope, C.1
Hicks, M.2
Lankamp, M.3
Poss, R.4
Zhang, L.5
-
3
-
-
33845209316
-
μTC - An intermediate language for programming chip multiproc-essors
-
4186 LNCS
-
C.R. Jesshope, "μTC - an intermediate language for programming chip multiproc-essors," in Asia-Pacific Computer Systems Architecture Conference, 4186 LNCS, 2006, pp. 147-160.
-
(2006)
Asia-pacific Computer Systems Architecture Conference
, pp. 147-160
-
-
Jesshope, C.R.1
-
4
-
-
33746252934
-
Microthreading a model for distributed instruction-level concur-rency
-
ISSN: 0129-6264
-
C. R. Jesshope, "Microthreading a model for distributed instruction-level concur-rency," Parallel processing Letters, vol.16, no. 2, 2006, pp. 209-228, ISSN: 0129-6264.
-
(2006)
Parallel Processing Letters
, vol.16
, Issue.2
, pp. 209-228
-
-
Jesshope, C.R.1
-
5
-
-
0030232590
-
Dynamic scheduling in RISC architectures
-
A. Bolychevsky, C. R. Jesshope and V. B. Muchnick, "Dynamic scheduling in RISC architectures," IEE Trans. E, Computers and Digital Techniques, 143, 1996, pp. 309-317.
-
(1996)
IEE Trans. E, Computers and Digital Techniques
, vol.143
, pp. 309-317
-
-
Bolychevsky, A.1
Jesshope, C.R.2
Muchnick, V.B.3
-
6
-
-
0015195766
-
Hierarchical ordering of sequential processes
-
June
-
E. W. Dijkstra, "Hierarchical ordering of sequential processes," Acta Informatica, vol. 1, no. 2, June 1971, pp. 115-138.
-
(1971)
Acta Informatica
, vol.1
, Issue.2
, pp. 115-138
-
-
Dijkstra, E.W.1
-
7
-
-
61749094459
-
Implementation and evaluation of a microthread architecture
-
Bousias, K., Guang, L., Jesshope, C., and Lankamp, "M. Implementation and Evaluation of a Microthread Architecture," Journal of Systems Architecture 55, 3 (2009), pp.149-161.
-
(2009)
Journal of Systems Architecture
, vol.55
, Issue.3
, pp. 149-161
-
-
Bousias, K.1
Guang, L.2
Jesshope, C.3
Lankamp, M.4
-
8
-
-
0024751383
-
I-structures: Data structures for parallel computing
-
Arvind, R. S. Nikhil, and K. K. Pingali, "I-structures: data structures for parallel computing," ACM Trans. Program. Lang. Syst., vol. 11, no. 4, 1989, pp. 598-632.
-
(1989)
ACM Trans. Program. Lang. Syst.
, vol.11
, Issue.4
, pp. 598-632
-
-
Arvind1
Nikhil, R.S.2
Pingali, K.K.3
-
10
-
-
33747508171
-
SAC: A functional array language for efficient multithreaded execution
-
C. Grelck and S-B. Scholz., "SAC: A functional array language for efficient multithreaded execution," International Journal of Parallel Programming, vol. 34, no. 4, 2006, pp. 383-427.
-
(2006)
International Journal of Parallel Programming
, vol.34
, Issue.4
, pp. 383-427
-
-
Grelck, C.1
Scholz, S.-B.2
-
11
-
-
44649176925
-
A gentle introduction to S-net: Typed stream processing and declarative coordination of asynchronous compo-nents
-
C. Grelck, S-B Scholz, and A. Shafarenko, "A gentle introduction to S-Net: Typed stream processing and declarative coordination of asynchronous compo-nents," Parallel Processing Letters, vol. 18, no. 1, 2008, pp.221-237.
-
(2008)
Parallel Processing Letters
, vol.18
, Issue.1
, pp. 221-237
-
-
Grelck, C.1
Scholz, S.-B.2
Shafarenko, A.3
-
14
-
-
83455182650
-
Lazy reference counting for the micro grid
-
April Chamonix, France, in press
-
R.C. Poss, and C.R. Jesshope, "Lazy Reference Counting for the Micro grid," CGO'10 April, 2011, Chamonix, France, in press.
-
(2011)
CGO'10
-
-
Poss, R.C.1
Jesshope, C.R.2
-
15
-
-
78049338046
-
-
Intel Corporation
-
Intel Corporation, Single-chip Cloud Computer, http://techresearch.intel. com/projectdetails.aspx?id=1
-
Single-chip Cloud Computer
-
-
|