Implementation and evaluation of a microthread architecture

Journal of Systems Architecture

Volumn 55, Issue 3, 2009, Pages 149-161

  Bousias, K ^a   Guang, L ^a   Jesshope, C R ^a   Lankamp, M ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

Architecture; Evaluation; Implementation; Microgrid; Microthread; SVP

Indexed keywords

REDUCED INSTRUCTION SET COMPUTING; SCALABILITY;

EVALUATION; IMPLEMENTATION; MICROGRID; MICROTHREAD; SVP;

MODEL STRUCTURES;

EID: 61749094459     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2008.07.001     Document Type: Article

References (18)

1. Aether Project. .
2. KSR1 technical summary, Technical Report, K.S.R. Corporation, 1992.
3. Inside Intel Itanium 2 processor: an Itanium processor family member for balanced performance over a wide range of applications, Technical White Paper, Hewlett Packard, July 2002.
4. International technology roadmap for semiconductors update, Technical Report, Semiconductor Industry Association, 2006.
5. A. Ali, L. Johnsson, J. Subhlok, Scheduling FFT computation on SMP and multicore systems, in: Proceedings of the 21st Annual International Conference on Supercomputing, 2007, pp. 293-301.
6. K. Asanovic, R. Bodik, B.C. Catanzaro, J.J. Gebis, P. Husbands, K. Keutzer, D.A. Patterson, W.L. Plishker, J. Shalf, S.W. Williams, K.A. Yelick, The landscape of parallel computing research: a view from Berkeley, Technical Report, EECS Department, University of California, Berkeley, 2006.
7. Bolychevsky A., Jesshope C.R., and Muchnick V.B. Dynamic scheduling in RISC architectures. IEE Transactions E: Computers and Digital Techniques 143 (1996) 309-317
8. Gao G.R., and Sarkar V. Location consistency-a new memory model and cache consistency protocol. IEEE Transactions on Computers 49 8 (2000) 798-813
9. S. Gupta, S.W. Keckler, D. Burger, Technology independent area and delay estimates for microprocessor building blocks, Technical Report, Computer Architecture and Technology Laboratory, 2000.
10. Hagersten E., Landin A., and Haridi S. DDM-a cache-only memory architecture. IEEE Computer 25 9 (1992) 44-54
11. Hammond L., Carlstrom B.D., Wong V., Chen M., Kozyrakis C., and Olukotun K. Transactional coherence and consistency: simplifying parallel hardware and software. IEEE Micro 24 6 (2004) 92-103
12. C.R. Jesshope, μTC-an intermediate language for programming chip multiprocessors, in: ACSAC06, LNCS 4186, 2006, pp. 147-160.
13. Kahle J.A., Day M.N., Hofstee H.P., Johns C.R., Maeurer T.R., and Shippy D. Introduction to the Cell multiprocessor. IBM Journal of Research and Development 49 4 (2005) 589-604
14. McGhan H. Niagara 2 opens the floodgates. Microprocessor Report 20 11 (2006) 1-12
15. Sinhary B., Kalla R.N., Tender J.M., Eickenmeyer R.J., and Joyner J.B. Power5 system microarchitecture. IBM Journal of Research and Development 49 4 (2005) 505-521
16. D. Tarjan, S. Thoziyoor, N.P. Jouppi, Cacti 4.0, Technical Report, Western Research Laboratory, Compaq, 2006.
17. Trancoso P., Evripidou P., Stavrou K., and Kyriacou C. A case for chip multiprocessors based on the data-driven multithreading model. International Journal of Parallel Program 34 3 (2006) 213-235
18. L. Zhang, C.R. Jesshope, On-chip COMA cache-coherence protocol for microgrids of microthreaded cores, in: Proceedings of the Workshop on Highly Parallel Processing on a Chip (HPPC), 2007.