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Volumn 51, Issue 5 I, 2004, Pages 1968-1973

SVX4: A new deep-submicron readout IC for the tevatron collider at fermilab

Author keywords

Analog digital conversion; Application specific integrated circuits; CMOS integrated circuits; Mixed analog digital integrated circuits; Particle tracking; Radiation detector circuits

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CAPACITANCE; COLLIDING BEAM ACCELERATORS; DETECTORS; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; TRANSCEIVERS; TRANSISTORS;

EID: 8344272923     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.836027     Document Type: Article
Times cited : (18)

References (6)
  • 2
    • 0033207650 scopus 로고    scopus 로고
    • The SVX3D integrated circuit for dead-timeless silicon strip readout
    • Oct.
    • M. Garcia-Sciveres et al., "The SVX3D integrated circuit for dead-timeless silicon strip readout," Nucl. Instr. Meth. A, vol. 435, pp. 58-64, Oct. 1999.
    • (1999) Nucl. Instr. Meth. A , vol.435 , pp. 58-64
    • Garcia-Sciveres, M.1
  • 3
    • 0032064090 scopus 로고    scopus 로고
    • A dead-timeless readout chip for silicon strip detectors
    • May
    • T. Zimmerman et al., "A dead-timeless readout chip for silicon strip detectors," Nucl. Instr. Meth. A, vol. 409, pp. 369-374, May 1998.
    • (1998) Nucl. Instr. Meth. A , vol.409 , pp. 369-374
    • Zimmerman, T.1
  • 4
    • 8344287952 scopus 로고    scopus 로고
    • FEI-2: A frontend readout chip designed in a commercial 0.25 μm process for the ATLAS pixel detector at LHC
    • Portland, OR, Oct.
    • L. Blanquart et al., "FEI-2: A frontend readout chip designed in a commercial 0.25 μm process for the ATLAS pixel detector at LHC," presented at the IEEE Nuclear Science Symp., Portland, OR, Oct. 2003.
    • (2003) IEEE Nuclear Science Symp.
    • Blanquart, L.1
  • 5
    • 0033311541 scopus 로고    scopus 로고
    • Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: Practical design aspects
    • Dec.
    • G. Anelli et al., "Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: Practical design aspects," IEEE Trans. Nucl. Sci, vol. 46, pp. 1690-1696, Dec. 1999.
    • (1999) IEEE Trans. Nucl. Sci , vol.46 , pp. 1690-1696
    • Anelli, G.1
  • 6
    • 0030375853 scopus 로고    scopus 로고
    • Upset hardened memory design for submicron CMOS technology
    • Dec.
    • T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, pp. 2874-2878, Dec. 1996.
    • (1996) IEEE Trans. Nucl. Sci. , vol.43 , pp. 2874-2878
    • Calin, T.1    Nicolaidis, M.2    Velazco, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.