DIALOG and SYNC: A VLSI chip set for timing of the LHCb muon detector

IEEE Transactions on Nuclear Science

Volumn 51, Issue 5 I, 2004, Pages 1961-1967

  Cadeddu, Sandro ^a   De Leo, Vincenzo ^a   Deplano, Caterina ^a   Lai, Adriano ^a  

^a SEZIONE DI CAGLIARI   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COLLIDING BEAM ACCELERATORS; DELAY CIRCUITS; DETECTORS; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; PROBLEM SOLVING; SIGNAL PROCESSING;

DETECTION EFFICIENCY; FRONT END CHANNEL DETECTION; LARGE HADRON COLLIDER (LHCB); MUON DETECTORS;

VLSI CIRCUITS;

EID: 8344252091     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.835574     Document Type: Article

References (7)

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3. P. Jarron et al., "Deep submicron CMOS technology for the LHC experiments," Nucl. Phys. B, vol. 78, no. 1-3, pp. 625-634, Aug. 1999.
4. S. Cadeddu and A. Lai, "DIALOG-β DATA SHEET," LHCb note-16, 2003.
5. 2 C-Bus Specifications v 2.1," Philips Semiconductor, 2000.
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7. C.-Y. Yang and S.-I. Liu, "A one-wire approach for skew-compensating clock distribution based on bidirectional techniques," IEEE J. Solid-State Circuits, vol. 36, Feb. 2001.