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Volumn , Issue , 2011, Pages 279-282
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Compensation of externally applied mechanical stress by stacking of ultra-thin chips
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Author keywords
[No Author keywords available]
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Indexed keywords
ACTIVE AREA;
ACTIVE LAYER;
ANALYTICAL MODEL;
APPLIED MECHANICAL STRESS;
CHIP THICKNESS;
CMOS DEVICES;
FLEXIBLE SYSTEM;
GLUE LAYERS;
MECHANICAL BENDING;
NEUTRAL LINE;
OPTIMUM THICKNESS;
SILICON CHIP;
STRESS COMPENSATION;
THIN CHIPS;
ULTRA-THIN CHIPS;
VISCOELASTIC BEHAVIORS;
CMOS INTEGRATED CIRCUITS;
GLUES;
GLUING;
MATHEMATICAL MODELS;
SOLID STATE DEVICES;
STRESSES;
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EID: 82955195094
PISSN: 19308876
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ESSDERC.2011.6044180 Document Type: Conference Paper |
Times cited : (7)
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References (6)
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