Multiple memristor read and write circuit for neuromorphic applications

Proceedings of the International Joint Conference on Neural Networks

Volumn , Issue , 2011, Pages 2676-2682

  Yakopcic, Chris ^a   Taha, Tarek M ^a   Subramanyam, Guru ^a   Rogers, Stanley ^b  

^a UNIVERSITY OF DAYTON   (United States)

^b AIR FORCE RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASIC BLOCKS; DEVICE CHARACTERIZATION; DISCRETE VALUES; MEMRISTOR; NEUROMORPHIC; NEURON SPIKE;

MEMRISTORS; NEURAL NETWORKS; RESISTORS;

PASSIVE FILTERS;

EID: 80054759109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2011.6033569     Document Type: Conference Paper

References (12)

1. L. O. Chua, Leon O, "Memristor-The Missing Circuit Element," IEEE Transactions on Circuit Theory, 18(5), 507-519 (1971).
2. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing Memristor found," Nature, 453, 80-83 (2008).
3. G. S. Snider, "Cortical Computing with Memristive Nanodevices," SciDAC Review, (2008).
4. Y. Ho, G. M. Huang, P. Li, "Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories," IEEE Transactions on Circuits and Systems I: Regular Papers, (2010).
5. D. Niu, Y. Chen, Y. Xie, "Low-power Dual-element Memristor Based Memory Design," ACM/IEEE International Symposium on Low-Power Electronics and Design, (2010).
6. Y. Ho, G. M. Huang, P. Li, "Nonvolatile Memristor Memory: Device Characteristics and Design Implications," IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, (2009).
7. H. Kim, M. P. Sah, C. Yang, L. O. Chua, "Memristor-based Multilevel Memory," 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), (2010).
8. th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), (2010).
9. M. Laiho, E. Lehtonen, "Cellular Nanoscale Network Cell with Memristors for Local Implication Logic and Synapses," IEEE International Symposium on Circuits and Systems, (2010).
10. J. A. Perez-Carrasco, C. Zamarreno-Ramos, T. Serrano-Gotarredona, B. Linares-Barranco, "On Neuromorphic Spiking Architectures for Asynchronous STDP Memristive Systems," Proceedings of IEEE International Symposium on Circuits and Systems, (2010).
11. E. M. Izhikevich, "Simple Model of Spiking Neurons," IEEE Transactions on Neural Networks, 14(6), (2003).
12. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," Nano Letters, 10 (2010).