A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages

  Kim, Jonghong ^a   Cho, Junhee ^a   Sung, Wonyong ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CELL SIZE; CHIP AREAS; CMOS PROCESSS; CODE RATES; ERROR PERFORMANCE; FIXED POINT ARITHMETIC; HIGH-SPEED; LDPC DECODER; LOW DENSITY PARITY CHECK; MIN-SUM; MIN-SUM DECODING; MINIMUM DISTANCE; MULTILEVEL CELL; NAND FLASH MEMORY; PROCESSING UNITS; QUANTIZATION ERRORS; QUASI-CYCLIC; SERIAL ARCHITECTURE; WORD-LENGTH REDUCTION;

CMOS INTEGRATED CIRCUITS; CODING ERRORS; DECODING; MEMORY ARCHITECTURE; NAND CIRCUITS; OPTIMIZATION; PARALLEL ARCHITECTURES; STATIC RANDOM ACCESS STORAGE;

FLASH MEMORY;

EID: 80053654770     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2011.6026357     Document Type: Conference Paper

References (7)

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