Experimental and numerical results correlation during extreme use of power MOSFET designed for avalanche functional mode

Microelectronics Reliability

Volumn 50, Issue 9-11, 2010, Pages 1804-1809

  Dupont, L ^a   Blanchard, J L ^b   Lallemand, R ^a   Coquery, G ^a   Morelle, J M ^b   Blondel, G ^b   Rouleau, B ^b  

^a UNIVERSITÉ GUSTAVE EIFFEL   (France)

^b VALEO   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AVALANCHE MODE; CONDUCTION MODE; ELECTRO-THERMAL SIMULATION; EXTREME CONDITIONS; FAST DYNAMICS; FINITE ELEMENT; HYBRID VEHICLES; MOS-FET; NUMERICAL MODELS; NUMERICAL RESULTS; POWER MOSFET; SIZE REDUCTIONS; SOLDER VOID;

TEMPERATURE DISTRIBUTION; TEMPERATURE MEASUREMENT; THERMOANALYSIS;

MOSFET DEVICES;

EID: 80052956708     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.07.127     Document Type: Conference Paper

References (5)

1. M. Ciappa Selected failure mechanisms of modern power modules Microelectron Reliab 42 2002
2. Saint-Eve F, Lefebvre S, Khatir Z. Reliability of COOLMOSTM under extremely hard repetitive electrical working conditions. In: IEEE ISPSD 03. Cambridge UK; April 2003.
3. B. Bernoux, R. Escoffier, P. Jalbaud, and J.M. Dorkel Source electrode evolution of a low voltage power MOSFET under avalanche cycling Microelectron Reliab 49 2009 1341 1345
4. McGloin J, Sdrulla D. Estimating the temperature rise of power MOSFETs during the UIS test. In: Proceeding of APEC; 1992. p. 448-53.
5. T.E. Salem, D. Ibitayo, and B. Geil Validation of infrared camera thermal measurements on high-voltage power electronic components IEEE Trans Instrum Measure 56 5 2007 1973 1978