A 10-bit 200 MS/s CMOS parallel pipeline A/D converter

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 439-442

  Sumanen, Lauri ^a   Waltari, Mikko ^a   Halonen, Kari ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; DIGITAL OFFSETS; DOUBLE SAMPLING; PARALLEL PIPELINE ADC; PIPELINE A/D CONVERTER; S/H CIRCUIT; SAMPLE RATE; SAMPLE-AND-HOLD CIRCUITS;

CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS;

PIPELINES;

EID: 80052714455     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. K.Y. Kim, N. Kusayanagi, A. Abidi, "A 10-b, 100-MS/s CMOS A/D Converter," IEEE J. Solid State Circuits, vol. SC-32, pp. 302-311, Mar. 1997.
2. L. Sumanen, M. Waltari, K. Halonen, "Optimizing the Number of Parallel Channels and the Stage Resolution in Time Interleaved Pipeline A/D Converters", accepted to ISCAS' 00, May 2000.
3. C.S.G. Conroy, D.W. Cline, P.R.Gray, "An 8-b 85-MS/s Parallel Pipeline A/D Converter in 1-mCMOS", IEEE J. Solid State Circuits, vol. SC-28, pp. 447-454, Apr. 1993.
4. S. Zarabadi, M. Ismail, "High Density Integrated Circuit with High Output Impedance", U.S. Pat. 5337021, 1994.
5. M. Waltari, K. Halonen, "Timing Skew Insensitive Switching for Double-Sampled Circuits", Proc. ISCAS'99, Jun. 1999, Vol.II, pp. 61-64.
6. M. Dessouky, A. Kaiser, "Input switch configuration for rail-to-rail operation of switched opamp circuits", Electronics Letters, vol. 35, no. 1, pp. 8-10, Jan 1999.