Optimizing the number of parallel channels and the stage resolution in time interleaved pipeline A/D converters

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2000, Pages

  Sumanen, Lauri ^a   Waltari, Mikko ^a   Halonen, Kari ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS;

PARALLEL CHANNELS;

DELTA SIGMA MODULATION;

EID: 0033683145     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.857518     Document Type: Conference Paper

References (4)