A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 74-75

  Chang, Meng Fan ^a   Wu, Wei Cheng ^a   Lin, Chih Sheng ^b   Chiu, Pi Feng ^b   Chen, Ming Bin ^a,b   Chen, Yen Huei ^a,c   Lai, Hsin Chi ^b   Lin, Zhe Hui ^b   Sheu, Shyh Shyuan ^b   Ku, Tzu Kun ^b   Yamauchi, Hiroyuki ^d  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^d FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTANT LOADS; DIE-TO-DIE VARIATIONS; LAYER CONFIGURATION; SELF-TIMED; SIGNAL TRANSFER; SRAM MACRO; STACKED LAYER;

DIES; THREE DIMENSIONAL; VLSI CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 80052690947     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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