3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 256-257

  Osada, Kenichi ^a   Saen, Makoto ^a   Okuma, Yasuyuki ^a   Niitsu, Kiichi ^b   Shimazaki, Yasuhisa ^b,c   Sugimori, Yasufumi ^b   Kohama, Yoshinori ^b   Kasuga, Kazutaka ^b   Nonomura, Itaru ^c   Irie, Naohiko ^a   Hattori, Toshihiro ^c   Hasegawa, Atsushi ^c   Kuroda, Tadahiro ^b  

^a HITACHI LTD   (Japan)

^b KEIO UNIVERSITY   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

3D system integration; Inductive coupling link; Memory; Processor

Indexed keywords

3D SYSTEM INTEGRATION; AREA EFFICIENCY; CHIP INTEGRATION; FABRICATED CHIPS; INDUCTIVE COUPLING LINK; INDUCTIVE COUPLINGS; LINK DISTANCE; LOWER-POWER CONSUMPTION; MEMORY; MEMORY CHIPS; MULTILAYER STRUCTURES; PROCESSOR; PROCESSOR CHIPS; SIGNAL DEGRADATION; SYSTEM INTEGRATION; THREE-DIMENSIONAL (3D);

VLSI CIRCUITS;

THREE DIMENSIONAL;

EID: 70449376846     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. K. Niitsu, et al., ISSCC Dig. Tech. Papers, 28.7, Feb. 2009.
2. M. Ito, et al., ISSCC Dig. Tech. Papers, pp. 90-91, Feb. 2008.
3. N. Niitsu, et al., JJAP, Vol. 46, No. 4B, pp. 2215-2219, Apr. 2007.