A 12b 3GS/s pipeline ADC with 500mW and 0.4 mm2 in 40nm digital CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 120-121

  Chen, Chun Ying ^a   Wu, Jiangfeng ^a  

^a BROADCOM CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; DIGITAL CMOS; PIPELINE ADCS;

CMOS INTEGRATED CIRCUITS; DIGITAL DEVICES; MOS DEVICES;

VLSI CIRCUITS;

EID: 80052650702     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S. Gupta et al., "A 1GS/s 11b Time-Interleaved ADC in 0.13um CMOS," ISSCC Digest of Technical Papers, pp. 2360-2369, Feb. 2006.
2. C-C. Hsu et al., "An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration," ISSCC Digest of Technical Papers, pp. 464-465, Feb. 2007.
3. R. Taft et al., "A 1.8V 1.0GS/s 10b Self-Calibrating Unified-Folding-Interpolation ADC with 9.1 ENOB at Nyquist Frequency," ISSCC Digest of Technical Papers, pp 78-79, Feb. 2009.
4. A. Verma et al., "A 10b 500MHz 55mW CMOS ADC," ISSCC Digest of Technical Papers, pp. 84-85, Feb. 2009.