Tomographic testing and validation of probabilistic circuits

Proceedings - 16th IEEE European Test Symposium, ETS 2011

Volumn , Issue , 2011, Pages 63-68

  Paler, Alexandru ^a   Alaghi, Armin ^b   Polian, Ilia ^a   Hayes, John P ^b  

^a UNIVERSITY OF PASSAU   (Germany)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCEPTABLE LIMIT; CIRCUIT UNDER TEST; COMPLEX CIRCUITS; EMERGING TECHNOLOGIES; ERROR MODEL; FAULT CONDITIONS; NANOELECTRONIC CIRCUITS; QUANTUM COMPUTING CIRCUITS; SOLUTION METHODS; STOCHASTIC CIRCUITS; TEST MEASUREMENTS; TOMOGRAPHIC;

COMPUTATIONAL LINGUISTICS; NANOELECTRONICS; QUANTUM COMPUTERS; QUANTUM THEORY; STOCHASTIC SYSTEMS;

PROBABILITY DISTRIBUTIONS;

EID: 80051964770     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2011.43     Document Type: Conference Paper

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