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Volumn , Issue , 2011, Pages 1672-1675

Thermal-aware energy minimization of 3D-stacked L3 cache with error rate limitation

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D-STACKED MEMORY; CHIP-MULTIPROCESSOR; EFFECTS OF TEMPERATURE; EMBEDDED DRAM; ENERGY MINIMIZATION; ERROR CORRECTING CODE; ERROR RATE; ERROR RATE CONSTRAINTS; HIGH POWER DENSITY; MEMORY BANDWIDTHS; PER UNIT VOLUME; SOFT ERROR; SYSTEM RELIABILITY; THREE-DIMENSIONAL (3D) MEMORY; VARYING TEMPERATURE;

EID: 79960875518     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5937902     Document Type: Conference Paper
Times cited : (11)

References (12)
  • 5
    • 49749103125 scopus 로고    scopus 로고
    • Dynamic voltage scaling of supply and body bias exploiting software runtime distribution
    • 10-14 March
    • Sungpack Hong, Sungjoo Yoo, Byeong Bin, Kyu-Myung Choi, Soo-Kwan Eo, Taehwan Kim, "Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution," Design, Automation and Test in Europe, 2008. DATE '08, vol., no., pp.242-247, 10-14 March 2008.
    • (2008) Design, Automation and Test in Europe, 2008. DATE '08 , pp. 242-247
    • Hong, S.1    Yoo, S.2    Bin, B.3    Choi, K.-M.4    Eo, S.-K.5    Kim, T.6
  • 6
    • 0032099759 scopus 로고    scopus 로고
    • On the retention time distribution of dynamic random access memory (DRAM)
    • Jun
    • T. Hamamoto, S. Sugiura, S. Sawada, "On the retention time distribution of dynamic random access memory (DRAM)," Electron Devices, IEEE Transactions on, vol.45, no.6, pp.1300-1309, Jun 1998.
    • (1998) Electron Devices, IEEE Transactions on , vol.45 , Issue.6 , pp. 1300-1309
    • Hamamoto, T.1    Sugiura, S.2    Sawada, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.