A 19 dBm 0.13μm CMOS parallel class-E switching PA with minimal efficiency degradation under 6 dB back-off

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2011, Pages

  Singhal, Nitesh ^a   Nidhi, Nitin ^a   Ghosh, Abhishek ^a   Pamarti, Sudhkar ^a  

^a Department of Civil and Environmental Engineering   (United States)

Author keywords

PA; PAE; PAR; PMR

Indexed keywords

A-CENTER; BACK-OFF; CLASS E; DIGITAL CMOS TECHNOLOGY; DRAIN EFFICIENCY; DUTY-CYCLE MODULATIONS; DYNAMIC RANGE; EFFICIENCY DEGRADATION; OUTPUT POWER; PAE; PAR; PARALLEL CLASS; PEAK EFFICIENCY; PEAK POWER; PMR;

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; DIGITAL RADIO; POWER AMPLIFIERS; RADIO; RADIO WAVES; ZERO VOLTAGE SWITCHING;

EFFICIENCY;

EID: 79960811653     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2011.5940714     Document Type: Conference Paper

References (6)

1. N. Singhal, N. Nidhi and S. Pamarti, "A Power Amplifier with Minimal Efficiency Degradation under back-off," Proceedings of 2010 IEEE ISCAS, pp. 1851-54, 2010.
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3. F. H. Raab, "High-efficiency linear amplification by dynamic load modulation," 2003 IEEE MTT-S International Microwave Symposium Digest, vol. 3, June 2003, pp. 1717-1720.
4. A. Kavousian, "A digitally modulated polar CMOS PA with 20 MHz signal BW," IEEE Journal of Solid-State Circuits, vol. 43, no. 10, pp. 2251-2258, October 2008.
5. D. Chowdhury, L.Ye, E. Alon, A. Niknejad, "A 2.4 GHz mixed Signal Polar Power Amplifier with Low Power integrated Filtering in 65nm CMOS," CICC, 2010 IEEE, pp. 1-4, 19-22 Sept. 2010.
6. P.E. Su and S. Pamarti, "A 2.4 GHz Wideband Open Loop GFSK Transmitter with Phase Quantization Noise Cancellation," accepted for publication in IEEE Journal of Solid State Circuits