A power amplifier with minimal efficiency degradation under back-off

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 1851-1854

  Singhal, Nitesh ^a   Nidhi, Nitin ^a   Pamarti, Sudhakar ^a  

^a Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BACK-OFF; CMOS PA; DESIGN AND SIMULATION; DRAIN EFFICIENCY; DYNAMIC RANGE; EFFICIENCY DEGRADATION; FREQUENCY OFFSETS; OUTPUT POWER; PEAK EFFICIENCY; SYSTEM LEVEL SIMULATION; ZERO VOLTAGE;

FREQUENCY ALLOCATION; POWER AMPLIFIERS; ZERO VOLTAGE SWITCHING;

FABRICS;

EID: 77955996339     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537819     Document Type: Conference Paper

References (13)

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