SystemC architectural transaction level modelling for large NoCs

IET Seminar Digest

Volumn 2010, Issue 2, 2010, Pages 142-147

  Hosseinabady, Mohammad ^a   Nunez Yanez, Jose L ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

HETEROGENEOUS CORES; MANY-CORE; MODELLING TECHNIQUES; NETWORK ON CHIP; PROCESS USE; SIMULATION TIME; SYSTEM EVALUATION; SYSTEM ON CHIPS; SYSTEM VALIDATION; SYSTEMC; TRANSACTION LEVEL;

COMPUTER SIMULATION; INDUSTRIAL APPLICATIONS; SPECIFICATIONS; VLSI CIRCUITS;

LOGIC DESIGN;

EID: 79960601867     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ic.2010.0143     Document Type: Conference Paper

References (12)

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