Design and characterization of power delivery system for multi-chip package with embedded discrete capacitors

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 2179-2184

  Cheng, Hung Hsiang ^a   Kuo, Chih Wen ^a   Pan, Po Chih ^b   Chen, Yi Hua ^b   Chen, Kuo Hua ^b   Li, Li ^c   Han, Ken ^c   Cooper, Glenn ^c  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

^c CISCO SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT BOARDS; COSIMULATION; DESIGN FEASIBILITY; EMBEDDED PASSIVES; FREQUENCY AND TIME DOMAINS; LOOP INDUCTANCE; MULTICHIP PACKAGES; PACKAGE SUBSTRATES; PEAK-TO-PEAK-; PLANAR CAPACITORS; POWER DELIVERY SYSTEMS; WELL DESIGN;

CHARACTERIZATION; DESIGN; ELECTRIC POWER TRANSMISSION;

CAPACITORS;

EID: 79960404467     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898821     Document Type: Conference Paper

References (4)

1. P. Muthana, E. Engin, P. M. Raj, M. Swaminathan, R. Tummala, V. Sundaram, D. Amey, K. Dietz, and S. Banerji, "Design, Modeling and Characterization of Embedded Capacitors for Decoupling Applications", in 7th Annual Austin CAS Conference, Feb. 2006.
2. L. Wan, P. M. Raj, M. Swaminathan, and R. Tummala, "Design, Simulation and Measurement Techniques for Embedded Decoupling Capacitors in Multi-GHz Packages/PCBs", ICEPT 2005, pp. 108-112, Aug. 2005.
3. K. Srinivasan, P. Muthana, R. Mandrekar, E. Engin, J. Choi, and M. Swaminathan, "Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages", ISQED 2006, pp. 286-291, Mar. 2006.
4. P. Muthana, A. E. Engin, M. Swaminathan, R. Tummala, V. Sundaram, B. Wiedenman, D. Amey, K. H. Dietz, and S. Banerji, "Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package", IEEE Trans. Adv. Package, vol. 30, pp. 809-822, Nov. 2007.