Deadlock-free fine-grained thread migration

NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2011, Pages 33-40

  Cho, Myong Hyon ^a   Shim, Keun Sup ^a   Lis, Mieszko ^a   Khan, Omer ^a   Devadas, Srinivas ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

on chip interconnection networks; thread migration protocols

Indexed keywords

INSTRUCTION-LEVEL; MEMORY COHERENCE; MIGRATION PROTOCOLS; MULTI-CORES; ON-CHIP INTERCONNECTION NETWORK; THREAD MIGRATION;

INTERCONNECTION NETWORKS; NETWORK ARCHITECTURE;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 79960334384     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1999946.1999952     Document Type: Conference Paper

References (17)

1. Moshe (Maury) Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, and Ady Tal. Analyzing parallel programs with pin. Computer, 43:34-41, 2010.
2. William J. Dally and Brian Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.
3. Wei Hu, Xingsheng Tang, Bin Xie, Tianzhou Chen, and Dazhou Wang. An efficient power-aware optimization for task scheduling on noc-based many-core system. In Proceedings of CIT 2010, pages 172-179, 2010.
4. Omer Khan, Mieszko Lis, and Srinivas Devadas. EM2: A Scalable Shared Memory Multi-Core Achitecture. In CSAIL Technical Report MIT-CSAIL-TR-2010-030, 2010.
5. Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Omer Khan, and Srinivas Devadas. Scalable directoryless shared memory coherence using execution migration. In CSAIL Technical Report MIT-CSAIL-TR-2010-053, 2010.
6. Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Pengju Ren, Omer Khan, and Srinivas Devadas. DARSIM: a parallel cycle-level NoC simulator. In Proceedings of MoBS-6, 2010.
7. M. Marchetti, L. Kontothanassis, R. Bianchini, and M. Scott. Using simple page placement policies to reduce the cost of cache fills in coherent shared-memory systems. In IPPS, 1995.
8. Steve Melvin, Mario Nemirovsky, Enric Musoll, and Jeff Huynh. A massively multithreaded packet processor. In Proceedings of NP2: Workshop on Network Processors, 2003.
9. Jason E. Miller, Harshad Kasture, George Kurian, Charles Gruenwald, Nathan Beckmann, Christopher Celio, Jonathan Eastep, and Anant Agarwal. Graphite: A distributed parallel simulator for multicores. In Proceedings of HPCA 2010, pages 1-12, 2010.
10. Matthew Misler and Natalie Enright Jerger. Moths: Mobile threads for on-chip networks. In Proceedings of PACT 2010, pages 541-542, 2010.
11. Michael D. Powell, Arijit Biswas, Shantanu Gupta, and Shubhendu S. Mukherjee. Architectural core salvaging in a multi-core processor for hard-error tolerance. In Proceedings of ISCA 2009, pages 93-104, 2009.
12. Krishna K. Rangan, Gu-Yeon Wei, and David Brooks. Thread motion: Fine-grained power management for multi-core systems. In Proceedings of ISCA 2009, pages 302-313, 2009.
13. Daeho Seo, Akif Ali, Won-Taek Lim, Nauman Rafique, and Mithuna Thottethodi. Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks. In Proceedings of the 32nd Annual International Symposium on Computer Architecture (ISCA 2005), pages 432-443, 2005.
14. Kelly A. Shaw and William J. Dally. Migration in single chip multiprocessor. In Computer Architecture Letters, pages 12-12, 2002.
15. L. G. Valiant and G. J. Brebner. Universal schemes for parallel communication. In STOC '81: Proceedings of the thirteenth annual ACM symposium on Theory of computing, pages 263-277, 1981.
16. Boris Weissman, Benedict Gomes, Jürgen W. Quittek, and Michael Holtkamp. Efficient fine-grain thread migration with active threads. In Proceedings of IPPS/SPDP 1998, pages 410-414, 1998.
17. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: characterization and methodological considerations. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 24-36, 1995.