The new program/erase cycling degradation mechanism of NAND flash memory devices

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Fayrushin, Albert ^a   Seol, Kwang Soo ^a   Na, Jong Hoon ^a   Hur, Sung Hoi ^a   Choi, Jung Dal ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLING STRESS; DEGRADATION MECHANISM; FLOATING GATES; GATE EDGE; INVERSE RELATIONSHIP; MEMORY CELL; MIDGAP VOLTAGE; NAND FLASH MEMORY; NEGATIVE OXIDE CHARGE; NON-UNIFORM DISTRIBUTION; OXIDE CHARGE; POSITIVE SHIFT; PROGRAM AND ERASE; PROGRAM STATE; PROGRAM/ERASE; RELIABILITY MODEL; SOURCE/DRAIN JUNCTIONS; SUBTHRESHOLD SWING;

DEGRADATION; ELECTRON DEVICES; SEMICONDUCTOR STORAGE;

FLASH MEMORY;

EID: 77952330181     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424213     Document Type: Conference Paper

References (4)

1. Y.B. Park, D.K. Schroeder., "Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM", IEEE Trans. Electron Devices, Vol.45, #6, 1998, pp. 1361-1368.
2. J-D. Lee, J-H. Choi, D. Park, and K. Kim, "Effects of interface trap generation and annihilation on the data retention characteristics of Flash memory cells", IEEE Trans. Device and Mater. Reliability, Vol.4, #1, 2004, pp. 110-117.
3. M.C. Park, K.S. Kim, J.H. Park, and J.H. Choi, "Direct field effect of neghbouring cell transistor on cell-to-cell interference of NAND Flash cell arrays", IEEE Electron Device Letters, Vol.30, #2, 2009, pp.155-157.
4. L. Perniola et al, "Analytical model of the effects of a nonuniform distribution of stored charge on the electrical characteristics of discrete-trap nonvolatile memories", IEEE Trans.Nanotechnology, Vol.4, #3, 2005, pp. 360-368.